1. Field of the Invention
This invention relates to semiconductor integrated circuit devices having plenty of external I/O terminals for inputting and outputting data, and particularly to semiconductor integrated circuit devices in which data transfer circuits are provided between main storages and auxiliary storages being formed on same semiconductor substrates.
This application is based on Patent Application No. Hei 11-69308 filed in Japan, the content of which is incorporated herein by reference.
2. Description of the Related Art
In general, computer systems use semiconductor devices of large capacities, in which processing speeds are relatively slow and costs in manufacture are relatively low, as main storage devices. To suite requirements of the main storage devices, the computer systems frequently use general-purpose DRAMs (i.e., dynamic random-access memories).
In the computer systems in these days, engineers develop DRAMs, which construct main storage portions, to increase processing speeds to cope with high-speed performance of the systems (particularly, high-speed performance of MPUs or microprocessing units). However, increasing the speeds of the DRAMs do not sufficiently catch up with the high-speed performance of the MPUs. To compensate gaps between speeds of the DRAMs and MPUs, the engineers design the computer systems to include high-speed memories between the main storages and MPUs as auxiliary storages. Those auxiliary storages are generally called xe2x80x9ccache memoriesxe2x80x9d, which correspond to high-speed SRAMs (static random-access memories), ECLRAM (where xe2x80x9cECLxe2x80x9d stands for xe2x80x9cEmitter-Coupled Logicxe2x80x9d), etc.
In general, the cache memories are provided externally of the MPUs, or they are built in the MPUs. Recently, engineers pay attention to semiconductor storage devices, in which DRAMs constructing main storages and cache memories are formed on same semiconductor substrates. Related arts regarding the aforementioned semiconductor storage devices are disclosed by a variety of papers and documents, as follows:
Japanese Patent Application, First Publication No. Sho 57-20983 discloses an example of a memory chip, which is equipped with an internal port for connecting memory cells with a latch circuit to transfer data.
Japanese Patent Application, First Publication No. Sho 60-7690 discloses an example of a semiconductor memory, in which data of dynamic memory cells are transferred to static memory cells by transfer gates with respect to rows.
Japanese Patent Application, First Publication No. Sho 62-38590 discloses an example of a semiconductor memory device, in which data transfer is made between a DRAM and an SRAM with respect to rows.
Japanese Patent Application, First Publication No. Hei 1-146187 discloses an example of a semiconductor memory device incorporating a cache memory, in which data of memory cells are transferred to data registers by units of blocks by way of transfer gates, which are selected by a block decoder.
The semiconductor storage devices of the aforementioned related arts are sometimes called xe2x80x9ccache DRAMsxe2x80x9d because they contain DRAMs and cache memories. Or, they may be described in connection with xe2x80x9cCD-RAMsxe2x80x9d, for example. They are configured to enable bidirectional transfer data between SRAMs, functioning as cache memories, and DRAMs constructing main storages.
The aforementioned related arts suffer from drawbacks such as operational delays in data transfer due to cache mishit events, for example. So, engineers propose a variety of techniques regarding improvements to the semiconductor storage devices, as follows:
Japanese Patent Application, First Publication No. Hei 4-252486 discloses an example of a semiconductor memory device, in which data blocks are transferred from a DRAM array to an SRAM array as a cache memory.
Japanese Patent Application, First Publication No. Hei 4-318389 discloses an example of a data transfer device applied to a semiconductor storage device, in which data transfer is performed between a DRAM and an SRAM, wherein transfer data are rewritten as write data to allow access to the SRAM after completion of the data transfer to the DRAM to cope with a cache miswrite event.
Japanese Patent Application, First Publication No. Hei 5-2872 discloses an example of a semiconductor storage device, in which data transfer is performed between a DRAM and an SRAM by way of a bidirectional transfer gate circuit, wherein different paths are provided for the DRAM in writing and reading data respectively in a non-multiplex manner to allow data transfer from the DRAM to the SRAM at a high speed even in a cache-miss event.
The aforementioned techniques are characterized by incorporating bidirectional data transfer circuits, which are used to perform data transfer between DRAMs and SRAMs and which contain functions of latches and registers. So, each semiconductor storage device incorporating the aforementioned technique is designed such that first transfer of data being transferred from the SRAM to the DRAM can be performed simultaneously with second transfer of data being transferred from the DRAM to the SRAM. This enables data transfer (or copy-back) to be made faster in a cache mishit event.
However, the aforementioned techniques are disadvantageous in that an area of the bidirectional data transfer circuit is large enough to occupy an overall area of the semiconductor substrate. So, there is a limit in a number of the circuits being installed on the semiconductor substrate. As a result, there is a limit in a number of transfer bus lines being provided with respect to the semiconductor storage device. For this reason, a number of bits being transferred between a DRAM array and an SRAM array at once is limited to sixteen (bits). Generally speaking, a cache hit rate is reduced as a number of bits being transferred at once becomes small.
FIG. 46 shows a recent example of a memory system being equipped with multiple processing devices. Such a memory system of FIG. 46 suffers from a drawback in which a cache hit rate is reduced upon receipt of access requests from the multiple processing devices. The multiple access requests given from the multiple processing devices (or memory masters) are frequently connected with address requests with regard to different sets (or rows). If a CD-RAM or ED-RAM (where xe2x80x9cEDxe2x80x9d stands for xe2x80x9cExchangeable Diskxe2x80x9d) is used as a main memory (9115) shown in FIG. 46, the cache hit rate is reduced, so that the memory system as a whole is limited in high-speed performance. To cope with an increasing number of systems each having multiple processing devices (or memory masters) in these days, main memories should be designed to respond to multiple kinds of access requests rather than a single kind of memory access, which is conventionally made.
In addition to the aforementioned problems, engineers should consider other problems such as soft errors, which are caused to occur due to neutrons being introduced into very fine structures of memory cells in these days.
Conventionally, as a main course of occurrence of soft errors, scientists and engineers name alpha (xcex1) rays being produced by decays that occur on very small amounts of radioactive isotopes being contained in packages and wiring materials inside of semiconductor chips. As another cause, Dr. J. F. Ziegler names cosmic rays in 1979, which is discussed in a paper entitled xe2x80x9cEffect of cosmic rays on computer memoriesxe2x80x9d in Science, vol. 206, pp. 776-788, November 1979. However, scientists and engineers do not show interests on such a cause for a long time.
Recently, rapid developments of fine structures of memory cells press the scientists and engineers to observe modes regarding defectiveness of memory cells in which data of multiple bits are inverted due to soft errors, which are considered to be caused by cosmic rays. As a result, they show great interests in soft errors due to neutrons. A mechanism in occurrence of the soft errors due to neutrons is described as follows:
Cosmic rays collide with atoms of the atmosphere of the Earth to produce neutrons. When the neutrons being produced in the atmosphere collide with silicon (Si) atoms within a chip, recoil nucleuses of Si nucleuses are being produced, or charged particles are being produced due to nuclear transformation reactions. The charged particles exert influences on stored charges of the memory cell, so that soft errors are being caused to occur.
Influences and effects of neutrons on semiconductor memories are described in detail by several papers, as follows:
A paper entitled xe2x80x9cImpact of Neutron flux on Soft Errors in MOS Memoriesxe2x80x9d0 written by M. Akira Eto and members for IEDM 98 (or 1998 IEEE, which stands for Institute of Electrical and Electronics Engineers); and an article entitled xe2x80x9cSoft Error of Memory LSI, Actual Measurement of Effects on Cosmic Raysxe2x80x9d written in pp. 145-155 of a journal called xe2x80x9cNIKKEI ELECTRONICSxe2x80x9d, no. 672 published on Oct. 7, 1996 in Japan.
FIG. 47 shows comparison between a soft error made due to xcex1 rays and a soft error mode due to neutrons, wherein xe2x80x9cSERxe2x80x9d stands for xe2x80x9cSoft Error Ratexe2x80x9d. As shown in FIG. 47, remarkable differences are found in amounts of charges being produced with respect to soft errors due to xcex1 rays and soft errors due to neutrons. That is, an amount of charges being produced due to neutrons is approximately ten times greater than an amount of charges being produced due to xcex1 rays, which is described in a paper entitled xe2x80x9cCosmic Ray Neutron Induced Upsets as a Major Contributor to the Soft Error Rate of Current and Future Generation DRAMSxe2x80x9d for IEEE IRPS, 1996. Herein, comparison is made between the soft errors due to xcex1 rays and neutrons with respect to an error mode representative of an emergence manner of bit defectiveness. That is, bit defectiveness due to xcex1 rays tend to emerge by a unit of a single bit, while bit defectiveness due to neutrons tend to emerge by a unit of multiple bits. In addition, comparison is made between them with respect to possibility of corrections to be performed using error correct codes (or error correcting codes, ECC). That is, the bit defectiveness due to xcex1 rays can be corrected because it corresponds to a single bit. However, it is difficult to correct the bit defectiveness due to neutrons because there is a tendency to increase frequencies in emergence of the bit defectiveness corresponding to multiple bits. So, a more complicated ECC system will be required to correct the bit defectiveness due to neutrons.
Because of needs of applications of personal computers, engineers design memories such as DRAMs to have large capacities and capabilities of processing plenty of bits. In other words, as developments in large capacities of the memories progress, the memories tend to have complicated configurations dealing with plenty of bits, wherein a number of external I/O terminals for inputting and outputting data is increased from eight to sixteen and is further increased to thirty-two, for example. In general, in order to reduce electric power being consumed or increase access speeds, memory cell arrays are reduced in sizes and dimensions, so that each memory (e.g., DRAM) is being configured by multiple memory cell arrays. A best method in efficiency to read out data of plenty of bits from memory cell arrays is to select much data using a single select line, so that data are to be readout from the memory cell arrays at once. Normally, this is achieved by assignment of a same address on the memory cell arrays. That is, 4-bit data are read from each memory cell array, for example, so that read data are simultaneously output from different external I/O terminals respectively.
FIG. 48 shows a typical example of a layout of memory cells, which correspond to different external I/O terminals and which are mixed and arranged within memory cell arrays. This example has sixteen external I/O terminals in total. So, memory cells are arranged in each memory cell array in connection with sixteen external I/O terminals, respectively. Namely, the layout of FIG. 48 is mainly configured by four blocks or memory cell arrays being designated by reference numerals 1010, 1020, 1030 and 1040 respectively. Each block consists of four blocks, which are designated by reference numerals 1001, 1002, 1003 and 1004 respectively. In addition, each block contains memory cells corresponding to four external I/O terminals. For example, memory cells are arranged in a block 1001 in connection with different external I/O terminals I/O0 to I/O3 respectively.
FIG. 49 shows a memory cell array of the block 1001 (see FIG. 48) and its peripheral circuit configurations. In FIG. 49, the memory cell array consists of rows and columns, which are arranged regularly in an array form. Herein, each column corresponds to a unit being partitioned by dotted lines in the memory cell array and consists of two bit lines (e.g., BL0, BL0b), while each row corresponds to a word line that crosses the bit lines with a right angle. Memory cells are appropriately arranged at points of intersection being formed between word lines and bit lines. In addition, circuitry corresponding to a row decoder and a word driver is arranged in periphery adjoining the memory cell array and is connected with the word lines. It activates a single word line in response to an external address.
Sense amplifiers SAMP0, SAMP1, SAMP2 and SAMP3 are also arranged in periphery adjoining the memory cell array. Herein, each sense amplifier is connected with a pair of bit lines to amplify signals being read from corresponding memory cells. Concretely, the sense amplifier SAMP0 is connected with a pair of bit lines BL0, BL0b; the sense amplifiers SAMP1 is connected with a pair of bit lines BL1, BL1b; the sense amplifier SAMP2 is connected with a pair of bit lines BL2, BL2b; and the sense amplifier SAMP3 is connected with a pair of bit lines BL3, BL3b. In addition, paired data I/O lines (i.e., DL0, DL1, DL2, DL3) are wired in periphery of the memory cell array in parallel with the rows. Further, transfer gate (i.e., TG1, TG2, TG3, TG4) are appropriately inserted between the paired data I/O lines and the paired bit lines. Those transfer gates are controlled by a single select line YSW. The select line YSW is wired in parallel with the column of the memory cell array. For example, it is formed by a metal wiring layer of an uppermost layer in a semiconductor chip.
FIG. 49 merely shows four columns of the memory cell array. Actually, however, 1,024 columns are arranged in the memory cell array. For convenience"" sake, FIG. 49 omits illustration of detailed circuit configurations, in which the data I/O lines DL0-DL3 are connected with the external I/O terminals by way of write circuits and read circuits. To read out data of plenty bits from memory cells of one memory cell array, the aforementioned layout has a variety of advantages, as follows:
The data I/O lines are arranged outside of the memory cell array. So, it is possible to freely wire a necessary number of data I/O lines. In addition, the layout requires a minimal number of lines being required as the select line YSW. As a result, the layout is reduced in load capacity and is superior in operation speed and consumption of electric power.
The aforementioned layout inevitably concentrates columns to adjoin each other in connection with different external I/O terminals. So, relatively large charges being produced due to neutrons influence stored data of memory cells, which are read out different external I/O terminals within a same cycle. Thus, there is a high likelihood in which bit defectiveness is caused to occur due to the neutrons. As a result, the conventional system suffers from a problem in which probability in occurrence of bit defectiveness is extremely high with respect to adjoining columns.
In the aforementioned layout, columns containing memory cells corresponding to four different external I/O terminals are arranged to adjoin each other. This shows a high probability in occurrence of bit defectiveness in which four bits simultaneously become defective within sixteen bits corresponding to the external I/O terminals I/O0 to I/O15. As described above, if a number of defective bits increases on the external I/O terminals, read data should be greatly changed in content information. This may greatly affect processing of the processing device(s) inputting the data. A degree in changing the information becomes remarkably high as a number of defective bits increases on the external I/O terminals.
It is an object of the invention to provide a semiconductor integrated circuit device which is capable of promptly responding to access requests given from multiple memory masters without reducing a cable hit rate.
It is another object of the invention to provide a semiconductor integrated circuit deice which is capable of minimizing a number of defective bits appearing on external I/O terminals due to neutrons.
According to a first aspect of the invention, a semiconductor integrated circuit device is basically configured by external I/O terminals and at least a memory cell array in which memory cells are arranged in mixture in connection with at least two external I/O terminals. Herein, the memory cells are arranged in an array form consisting of rows and columns in connection with word lines and bit lines respectively, so that data are read out from the memory cell array and are output to the external I/O terminals. In addition, columns whose memory cells store data being read out to the external I/O terminals within a same cycle are arranged to be apart from each other. Further, bit lines respectively belonging to the columns are connected with data I/O lines by way of switching elements, which are controlled in conduction by select signal lines which are wired to extend in parallel with the rows, while the data I/O lines are wired to extending parallel with the columns. Furthermore, the data I/O lines are respectively connected with the bit lines of the columns which adjoin each other by way of the switching elements, which are controlled in conduction by different select signal lines.
According to the first aspect of the invention, the memory cells corresponding to different external I/O terminals are arranged not in a concentrated manner but in a dispersed manner. For this reason, even if charged particles are produced locally due to neutrons, there is a small probability in that the memory cells which are simultaneously subjected to read operations within a same cycle exist within a range of an area under influence of the charged particles. Therefore, even if data of the memory cells which are concentrated at a certain region are simultaneously placed under influence of the charged particles, it is possible to remarkably reduce a number of chances in which multiple bits of data being read out to the external I/O terminals go defective simultaneously.
According to a second aspect of the invention, a semiconductor integrated circuit device is configured by external I/O terminals, a main storage having at least a memory cell array in which memory cells are arranged in mixture in connection with at least two external I/O lines and in which the memory cells are arranged in an array form consisting of rows and columns in connection with word lines and bit lines respectively, and an auxiliary storage that functions as a cache memory for the main storage, so that bidirectional data transfer is allowed between the main storage and auxiliary storage. Herein, data are read out from the main storage and are output to the external I/O terminals by way of the auxiliary storage. In addition, columns whose memory cells store data being read out to the external I/O terminals within a same cycle are arranged to be apart from each other.
It is possible to configure the semiconductor integrated circuit device such that the memory cell array of the main storage includes columns which are arranged to adjoin each other in space in connection with the external I/O terminals respectively and each of which is commonly assigned with a first address. Herein, the columns are equipped with switching elements respectively. By selectively conducting the switching element in response to a second address, data are read out from any one of the columns and are output to any one of the external I/O terminals.
In the above, each of the memory cells belonging to each column is selected in response to the first address, while each column is being selected in response to the second address. That is, data of only one memory cell is selectively read out from among memory cells which are arranged to adjoin each other in space within a same cycle. In addition, memory cells belonging to columns which adjoin each other are not simultaneously subjected to read operations within the same cycle. Relationships between the external I/O terminals and columns are set in such a way that columns storing data which are read out to the external I/O terminals within the same cycle are not arranged to adjoin each other. For this reason, even if charged particles are produced locally due to neutrons, it is possible to remarkably reduce a number of chances in which multiple bits of data being read out to the external I/O terminals go defective simultaneously.
Incidentally, it is possible to configure the semiconductor integrated circuit device in such a way that columns which are not subjected to read operations within the same cycle are arranged to adjoin each other in the memory cell array. Thus, columns respectively containing memory cells which are simultaneously subjected to read operations within a same cycle are arranged to be apart from each other by intervention of another column containing memory cells which are subjected to read operations within another cycle. So, it is possible to provide some interval of distance between columns respectively containing memory cells which are subjected to read operations within the same cycle without reduction of integration in arrangement of memory cells.
Moreover, it is possible configure the semiconductor integrated circuit device in such a way that a parity bit is provided for error correction on each unit of data being read out to the external I/O terminals within the same cycle. Herein, a distance being formed between memory cells which are simultaneously subjected to read operations is set to exceed a range of an area under influence of charged particles due to neutrons. Thus, it is possible to suppress a number of bits whose data are simultaneously read out to the external I/O terminals and whose data go defective simultaneously to a single bit. In this case, it is possible to correct an error of the data due to neutrons by using the parity bit.